The fabrication of integrated circuits (ICs) involves the formation of features on a substrate that make up circuit components, such as transistors, resistors and capacitors. The devices are interconnected, enabling the IC to perform the desired functions. Interconnections are formed by forming contacts and conductive lines in a dielectric layer using, for example, damascene techniques.
As critical dimensions (CD) continue to shrink, RC delay contributed by back-end-of line (BEOL) interconnects becomes more and more significant. In the effort to introduce lower k dielectrics for BEOL interconnects, materials such as porous ultra low k (ULK) inter level dielectric (ILD) and lower k SiCN Copper (Cu) barrier material have been proposed. However, with the continuous decrease of k value, the dielectrics become structurally more porous with lower mechanical strength and fracture toughness. In addition, integration of Cu with ULK dielectrics in BEOL has issues such as difficulty in handling damage of ULK post RIE/ashing, cleaning, Cu Chemical Mechanical Polishing (CMP), or packaging.
From the foregoing discussion, it is desirable to provide a ULK integration scheme that is more robust and reliable.